paulsong86
Nov 29, 2010
Graduate / EE SOP for UW, Electric Machines and Power Electronics Consortium [3]
Hi,everyone, I want to apply MS/PHD to ECE at UW. Here is my SOP. Please kindly help me correct the essay. I really appreciate your help! Best Regards
"Stay humble, Stay foolish!" Steve Jobs told us never stop to explore the new world. Thinking creatively and turning the idea to fruit, I am always on my way to the unknown.
For the past two and a half years I have been studying as a PHD student in ESD lab of XX University. The passion to learn and the ability to deliberately conceive on trouble shooting have made me a dependable team player with 11 papers published on international journals and conferences such as IEEE Electron Device Lett.(EDL),Electron. Lett.(EL),IEEE Trans Dev. Mater. Reliab.(TDMR), MICROELECTRON. RELIAB.(MR),European Symposium on the Reliability of Electron Devices, Failure Physics and Analysis(ESREF),IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA),.
In retrospect, I perceive that life is a process of conscious evolution. The most essential part of this growth is an intrigued passion for science and the values imbibed in me by people I met. The passion for science guided me to major in microelectronics, which is a world full of innovations. This provides ample opportunities to take challenges. .
In undergraduate stage, the courses of microelectronics laid emphasis on Mathematics, Physics, Devices and IC Design, and gave me theoretical ability in problem analysis and solving. The state key laboratory of integrated optoelectronics of Jilin University is proud of its fabrication and testing facilities. We have opportunities to access these facilities to fabricate semiconductor devices step-by-step: oxidation, masking, etching, implanting, annealing and so on. When the correct I-V curve was obtained, I knew that I was on my way to design novel device.
Working on devices gave me a sound technical base, but the greatest advantage was that it benefited my electronic design, which turned the device and ICs into daily products. I led a group of three in Electronic Design Contest in XX University and won a third prize. We developed a multi-point temperature detection system based on Matlab environment. I was responsible for the design of Matlab GUI, data communication between Matlab and MCU, data processing and storing. Then I represented my university at the National Undergraduate Electronic Design Contest in 2007, responsible for signal detection circuit and processing based on MCU. I realized that I was on my way to design marvel circuit system.
Due to the outstanding academic records, ranking 5/59 in my major and enriched research experiences, I was admitted to XX University without examination in Oct. 2007. Then I worked as an undergraduate research student for my graduation thesis during Mar. 2008 and May 2008 in ESD lab of XX University. I was engaged in the characterization and data analysis of different failure level for GCNMOS under different test conditions. The failure analysis (FA) was conducted via ORBICH to confirm the hypothesis for the different failure level. A flaw of HBM ESD test standard was found and published in TDMR, entitled "A Case Study of Problems in JEDEC HBM ESD Test Standard"(Cited as "new findings on science" in Verticalnews).. After 3 month's hard work, I finished my graduation thesis and stepped into the world of advanced device design for ESD protection.
From Sept.2008, I started my research in graduate stage, which greatly develops my ability in device design. My research mainly focused on device design for ESD protection based on MOS, SCR, BJT and LDMOS. In the project of device design for ESD protection in 65nm CMOS process, I designed novel substrate-triggered GGNMOS with TCAD and Spectre simulator. Besides, I had discussion and evaluation with my colleagues in novel capacitance-coupling-triggered SCR. After the chip was fabricated, I characterized these devices with TLP, VF-TLP and DC curve tracer at room temperature and high temperature, respectively, Two journal papers were published based on the research such as: "Substrate-triggered GGNMOS in 65 nm CMOS process for ESD application," in EL, Apr.2010 (featured paper), "A Novel Capacitance-Coupling-Triggered SCR for Low-Voltage ESD Protection Applications," in EDL, Oct.2010.
The solid device research experience enabled me to get more findings. The current saturation behaviors in Dual Direction SCR (DDSCR) were discovered unexpectedly when I reviewed the test data of gradations. After TCAD simulation and analysis of working mechanism of DDSCR under high current stage, I selected the key factor contributed to the unique characteristic and taped out several test-keys. The results, verified my analysis, were published in MR, in press, entitled "Study of current saturation behaviors in dual direction SCR for ESD applications,"
Another project made me think more. I developed a novel SCR based devices with high holding voltage in 0.5m BCD process. With other performance quite satisfying, the leakage was very large for the punch through of device, thus it cannot be used because it would consume too much power. This disappointment, however, spurred me to think more serious about power. An idea to do research on power device and power system, which controls a large range of power, began to emerge. The idea was reinforced by a lecture about SiC power device and power system by Prof. Sheng, where its compact and high efficiency impressed me. However this calls for comprehensive research, I cannot pursue the idea while still carrying my current research. I know it is the right time to connect the dots. Hence I have decided to pursue my PHD degree in an environment focused on power device and system.
The Wisconsin Electric Machines and Power Electronics Consortium at ECE in UW have the best research facilities and professors in this domain. The research and development carried out in this center perfectly match my interest. I would like to carry out my research under the guidance of Prof. Lorenz, Prof. Venkataramanan and Prof. Han. Their areas of work are fascinated to me and I believe that I can prove to be an effective and reliable team member in carrying out cutting edge research under their supervisions.
Hi,everyone, I want to apply MS/PHD to ECE at UW. Here is my SOP. Please kindly help me correct the essay. I really appreciate your help! Best Regards
"Stay humble, Stay foolish!" Steve Jobs told us never stop to explore the new world. Thinking creatively and turning the idea to fruit, I am always on my way to the unknown.
For the past two and a half years I have been studying as a PHD student in ESD lab of XX University. The passion to learn and the ability to deliberately conceive on trouble shooting have made me a dependable team player with 11 papers published on international journals and conferences such as IEEE Electron Device Lett.(EDL),Electron. Lett.(EL),IEEE Trans Dev. Mater. Reliab.(TDMR), MICROELECTRON. RELIAB.(MR),European Symposium on the Reliability of Electron Devices, Failure Physics and Analysis(ESREF),IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA),.
In retrospect, I perceive that life is a process of conscious evolution. The most essential part of this growth is an intrigued passion for science and the values imbibed in me by people I met. The passion for science guided me to major in microelectronics, which is a world full of innovations. This provides ample opportunities to take challenges. .
In undergraduate stage, the courses of microelectronics laid emphasis on Mathematics, Physics, Devices and IC Design, and gave me theoretical ability in problem analysis and solving. The state key laboratory of integrated optoelectronics of Jilin University is proud of its fabrication and testing facilities. We have opportunities to access these facilities to fabricate semiconductor devices step-by-step: oxidation, masking, etching, implanting, annealing and so on. When the correct I-V curve was obtained, I knew that I was on my way to design novel device.
Working on devices gave me a sound technical base, but the greatest advantage was that it benefited my electronic design, which turned the device and ICs into daily products. I led a group of three in Electronic Design Contest in XX University and won a third prize. We developed a multi-point temperature detection system based on Matlab environment. I was responsible for the design of Matlab GUI, data communication between Matlab and MCU, data processing and storing. Then I represented my university at the National Undergraduate Electronic Design Contest in 2007, responsible for signal detection circuit and processing based on MCU. I realized that I was on my way to design marvel circuit system.
Due to the outstanding academic records, ranking 5/59 in my major and enriched research experiences, I was admitted to XX University without examination in Oct. 2007. Then I worked as an undergraduate research student for my graduation thesis during Mar. 2008 and May 2008 in ESD lab of XX University. I was engaged in the characterization and data analysis of different failure level for GCNMOS under different test conditions. The failure analysis (FA) was conducted via ORBICH to confirm the hypothesis for the different failure level. A flaw of HBM ESD test standard was found and published in TDMR, entitled "A Case Study of Problems in JEDEC HBM ESD Test Standard"(Cited as "new findings on science" in Verticalnews).. After 3 month's hard work, I finished my graduation thesis and stepped into the world of advanced device design for ESD protection.
From Sept.2008, I started my research in graduate stage, which greatly develops my ability in device design. My research mainly focused on device design for ESD protection based on MOS, SCR, BJT and LDMOS. In the project of device design for ESD protection in 65nm CMOS process, I designed novel substrate-triggered GGNMOS with TCAD and Spectre simulator. Besides, I had discussion and evaluation with my colleagues in novel capacitance-coupling-triggered SCR. After the chip was fabricated, I characterized these devices with TLP, VF-TLP and DC curve tracer at room temperature and high temperature, respectively, Two journal papers were published based on the research such as: "Substrate-triggered GGNMOS in 65 nm CMOS process for ESD application," in EL, Apr.2010 (featured paper), "A Novel Capacitance-Coupling-Triggered SCR for Low-Voltage ESD Protection Applications," in EDL, Oct.2010.
The solid device research experience enabled me to get more findings. The current saturation behaviors in Dual Direction SCR (DDSCR) were discovered unexpectedly when I reviewed the test data of gradations. After TCAD simulation and analysis of working mechanism of DDSCR under high current stage, I selected the key factor contributed to the unique characteristic and taped out several test-keys. The results, verified my analysis, were published in MR, in press, entitled "Study of current saturation behaviors in dual direction SCR for ESD applications,"
Another project made me think more. I developed a novel SCR based devices with high holding voltage in 0.5m BCD process. With other performance quite satisfying, the leakage was very large for the punch through of device, thus it cannot be used because it would consume too much power. This disappointment, however, spurred me to think more serious about power. An idea to do research on power device and power system, which controls a large range of power, began to emerge. The idea was reinforced by a lecture about SiC power device and power system by Prof. Sheng, where its compact and high efficiency impressed me. However this calls for comprehensive research, I cannot pursue the idea while still carrying my current research. I know it is the right time to connect the dots. Hence I have decided to pursue my PHD degree in an environment focused on power device and system.
The Wisconsin Electric Machines and Power Electronics Consortium at ECE in UW have the best research facilities and professors in this domain. The research and development carried out in this center perfectly match my interest. I would like to carry out my research under the guidance of Prof. Lorenz, Prof. Venkataramanan and Prof. Han. Their areas of work are fascinated to me and I believe that I can prove to be an effective and reliable team member in carrying out cutting edge research under their supervisions.