anudeep477
Nov 30, 2013
Graduate / I was highly motivated by the cutting edge research technologies; MS in VLSI- SOP [6]
With the ever increase in complexity of the VLSI systems today power consumption also increasing accordingly. So there is a necessity to implement low power techniques especially for power critical systems like Mobile,_____ etc .I aspire to work on challenging research areas of high performance architecture and low power digital VLSI domain through Master of Science degree in Electrical and Computer Engineering at the University of ______________.
Till my higher secondary schooling I always used to be overwhelmingly fascinated towards Mathematics and Physics. Because of that interest and diligent effort I always used to ace top in the class in these subjects. And I got 1300 All India Rank out of 800,000 students appeared for National level exam AIEEE. Because of my interest in Mathematics and Physics I chose Electronics and Communication Engineering as my major.
When I entered the sophomore year of the college, I got introduced to electronics courses like Electronics Devices and Circuits and Switching Theory and Logic Design. I was mesmerized by the scope of research in the field of Electronics when Assistant Professor J Ravi Kumar was explaining. Later on, I approached him to give a chance in research. But his Doctoral research was towards Kalman Filters in Control Systems. He then told these filters can be applied into the field of electronics. Then I worked under him for almost a year while pursuing my undergraduate studies. After working for a year, I presented a paper titled "A HYBRID GA-ADAPTIVE PARTICLE SWARM OPTIMIZATION BASED TUNING OF UNSCENTED KALMAN FILTER FOR HARMONIC ESTIMATION" on Springer link conference. In the International conference, I saw a lot of Professors giving guest lectures. I was so bewitched with the guest lectures given by Professors from International universities, and I developed a strong aptitude to pursue my research in the field of Electronics and computing engineering. Later on I used to give presentations to juniors about these research topics who are working under same lecturer, which enabled me to develop effective leadership skills. I was also involved in various technical and cultural spectra of college life which helped me to hone my communication skills.
In the third year, I was introduced to subjects like Pulse Circuits, Linear IC Applications, Digital IC Applications and Digital System Design. During Digital System Design Lab, I Implemented Channel Equalization using 3-tap FIR filters. FIR filter was designed using Floating Point Adder, Floating point Multiplier and D Flip-Flop. I implemented the Channel Equalization filter in FPGA. The same Channel Equalization algorithm I implemented in MATLAB by adding coloured noise as part of Digital Signal Processing Assignment. Here I found the beauty of implementing same concept in both hardware and software.
Coming to my Final year project, I was given to work under Sri. Muralidhar P. Fortunately, his doctoral research matched with my interests. I have gone through various research papers in the field of Video Compression. I thought of implementing same Genetic and Particle Swarm Optimization Algorithms for the Motion Estimation block in Video encoder. But, lack of time and sufficient hardware resource has hindered our project from moving towards research oriented work, although my passion for these novel ideas continues unabated. Finally I implemented Efficient Variable Block Size Motion Estimation Architecture for H.264/AVC Video Codec in FPGA.
When I entered the industry, I was exposed to various activities involved from front end to back end in whole ASIC design. After trainings, I was on my team and I have gone through all the System architectures in the SoC domain related to Cypress Semiconductors. Later, I was given AHB Bus Protocol IP. Initially, I have written System Verilog Assertions for all public cells. Later, I did all activities like Lint, Formality, Synthesis and Silicon Validation. Then, I have written System Verilog Assertions and Benchmarking for Flash Controller. After IP, I worked on full-chip project. In full-chip I had written top-level RTL, performed Lint, CDC, Synthesis, Formality and MVRC. Apart from a firm knowledge of System level Architecture and tools I am also proficient at scripting languages like TCL, Perl and Hardware description languages like VHDL and Verilog.
I was highly motivated by the cutting edge research technologies at the ______________ research labs in your department ______________ under Prof _______ and staff __________. I found my research interest match with the research going on your department.
With the ever increase in complexity of the VLSI systems today power consumption also increasing accordingly. So there is a necessity to implement low power techniques especially for power critical systems like Mobile,_____ etc .I aspire to work on challenging research areas of high performance architecture and low power digital VLSI domain through Master of Science degree in Electrical and Computer Engineering at the University of ______________.
Till my higher secondary schooling I always used to be overwhelmingly fascinated towards Mathematics and Physics. Because of that interest and diligent effort I always used to ace top in the class in these subjects. And I got 1300 All India Rank out of 800,000 students appeared for National level exam AIEEE. Because of my interest in Mathematics and Physics I chose Electronics and Communication Engineering as my major.
When I entered the sophomore year of the college, I got introduced to electronics courses like Electronics Devices and Circuits and Switching Theory and Logic Design. I was mesmerized by the scope of research in the field of Electronics when Assistant Professor J Ravi Kumar was explaining. Later on, I approached him to give a chance in research. But his Doctoral research was towards Kalman Filters in Control Systems. He then told these filters can be applied into the field of electronics. Then I worked under him for almost a year while pursuing my undergraduate studies. After working for a year, I presented a paper titled "A HYBRID GA-ADAPTIVE PARTICLE SWARM OPTIMIZATION BASED TUNING OF UNSCENTED KALMAN FILTER FOR HARMONIC ESTIMATION" on Springer link conference. In the International conference, I saw a lot of Professors giving guest lectures. I was so bewitched with the guest lectures given by Professors from International universities, and I developed a strong aptitude to pursue my research in the field of Electronics and computing engineering. Later on I used to give presentations to juniors about these research topics who are working under same lecturer, which enabled me to develop effective leadership skills. I was also involved in various technical and cultural spectra of college life which helped me to hone my communication skills.
In the third year, I was introduced to subjects like Pulse Circuits, Linear IC Applications, Digital IC Applications and Digital System Design. During Digital System Design Lab, I Implemented Channel Equalization using 3-tap FIR filters. FIR filter was designed using Floating Point Adder, Floating point Multiplier and D Flip-Flop. I implemented the Channel Equalization filter in FPGA. The same Channel Equalization algorithm I implemented in MATLAB by adding coloured noise as part of Digital Signal Processing Assignment. Here I found the beauty of implementing same concept in both hardware and software.
Coming to my Final year project, I was given to work under Sri. Muralidhar P. Fortunately, his doctoral research matched with my interests. I have gone through various research papers in the field of Video Compression. I thought of implementing same Genetic and Particle Swarm Optimization Algorithms for the Motion Estimation block in Video encoder. But, lack of time and sufficient hardware resource has hindered our project from moving towards research oriented work, although my passion for these novel ideas continues unabated. Finally I implemented Efficient Variable Block Size Motion Estimation Architecture for H.264/AVC Video Codec in FPGA.
When I entered the industry, I was exposed to various activities involved from front end to back end in whole ASIC design. After trainings, I was on my team and I have gone through all the System architectures in the SoC domain related to Cypress Semiconductors. Later, I was given AHB Bus Protocol IP. Initially, I have written System Verilog Assertions for all public cells. Later, I did all activities like Lint, Formality, Synthesis and Silicon Validation. Then, I have written System Verilog Assertions and Benchmarking for Flash Controller. After IP, I worked on full-chip project. In full-chip I had written top-level RTL, performed Lint, CDC, Synthesis, Formality and MVRC. Apart from a firm knowledge of System level Architecture and tools I am also proficient at scripting languages like TCL, Perl and Hardware description languages like VHDL and Verilog.
I was highly motivated by the cutting edge research technologies at the ______________ research labs in your department ______________ under Prof _______ and staff __________. I found my research interest match with the research going on your department.
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