Aditya_K
Nov 23, 2025
Letters / Letter of Motivation for MS in Electrical Engineering at ETH Zurich [2]
I have written a motivational letter for my Master's application in Electrical and Computer Engineering, with a strong focus on VLSI and Digital Design. I would appreciate honest, detailed feedback regarding the structure, clarity, flow, and impact overall, including how well it conveys motivation and technical readiness.
Full Motivational Letter:
My fascination with electronic systems began in childhood, when I would often visit my father's computer sales and service business out of curiosity, watching how components like the CPU, GPU, and memory together powered entire systems. Those early observations sparked a lasting passion to understand how complex electronic architectures emerge from the interaction of such fundamental building blocks. Over time, this curiosity evolved into a deep interest in understanding how devices are built-from the physics of transistors to the architecture of complex systems-and how every advancement in semiconductor fabrication presents new challenges and opportunities for circuit designers to innovate. Visiting semiconductor cleanrooms in India and Taiwan reinforced this realization, as I witnessed the immense precision and difficulty involved in pushing technology toward ever smaller and more efficient scales. The constant drive to optimize circuits by reducing power consumption, minimizing component size, and improving performance speed gives this field a distinct edge and limitless potential for innovation. This relentless pursuit of improvement appeals to the engineer and problem-solver in me, motivating me to deepen my expertise in Electrical and Computer Engineering. Through my academic journey and internship experiences, I have realized that this domain demands a profound level of expertise to make significant contributions. To bridge the gap between theoretical advancements and practical implementations and to fulfil my aspiration of driving innovation in circuit design, I aim to pursue a master's degree that will equip me with advanced knowledge, cutting-edge skills, and practical exposure to enhance the impact of my work in this domain.
My primary areas of interest include VLSI, Digital Logic Design, and Embedded Systems. As an undergraduate student in Electronics and Communication Engineering at IIT Roorkee, my journey began with foundational courses such as Analog Circuits, Digital Logic Design, and Microelectronic Devices and IC Applications These courses helped me develop a strong conceptual understanding of circuit design, device behaviour, and embedded architectures. In these courses, through various projects, I explored full-custom VLSI design using Cadence Virtuoso, where I created schematic layouts and performed DRC, LVS, and PEX verification for logic gates, flip-flops, and ring oscillators using 180nm technology. I also designed a two-stage CMOS operational amplifier in LTSpice and carried out PMOS simulations in Synopsys Sentaurus TCAD, analysing threshold voltage, subthreshold slope, and DIBL variations across technology nodes-an experience that strengthened my grasp of the trade-offs between performance, power, and area in modern circuits. Moving from transistor-level design to digital implementation, I developed the RTL design of combinational and sequential logic circuits using Verilog, verified them on FPGA platforms, and gained insights into timing optimization, resource mapping, and custom block design. My understanding of embedded architectures deepened as I programmed the 8085 microprocessors, which strengthened my understanding of instruction-level execution and embedded control. Furthermore, I co-developed a real-time passenger counting system using edge computing and deep learning-an innovation that led to a patent publication (IN202411xxxx). This project's blend of algorithm design, embedded hardware, and system integration reinforced my interest in complete electronic system development.
A defining moment in my journey was being selected among 25 students nationwide for the Indo-Taiwan Semiconductor Workforce Development Program, jointly conducted by XXX and National Tsing Hua University (NTHU), Taiwan. Under the mentorship of TSMC engineers and NTHU professors, I gained hands-on exposure to semiconductor fabrication processes, lithography, and advanced packaging techniques such as CoWoS, FOWLP, and 3D IC stacking. Observing the precision and challenges of sub-nanometre fabrication deepened my appreciation for how fabrication constraints drive innovation in circuit design, strengthening my resolve to specialize in VLSI design. Beyond academics, I served as the Joint Secretary of ASME IIT Roorkee, where I led projects integrating electronics, control systems, and embedded hardware. Working with Raspberry Pi, Arduino, hardware accelerators, and Pixhawk autopilot modules, I helped develop an Autonomous Underwater Vehicle (AUV) for international competitions. Our team achieved 2ⁿᵈ place in India and 8ᵗʰ globally at SAUVC 2024, an experience that honed my collaborative problem-solving and system-level thinking.
Building on the insights gained, I am currently working on my B.Tech project which focuses on the design of an SPI interface chip in TSMC 65 nm technology under the supervision of Dr.XXX encompassing the full RTL-to-GDSII design flow. I successfully implemented the RTL design as per the required specifications using Verilog in Xilinx Vivado, verified it through simulation, and deployed it on an FPGA platform for functional validation. The design was later synthesized using Cadence Genus, followed by floor planning, placement, and routing, and I am currently working on Clock Tree Synthesis and its optimization to minimize skew and power consumption, This gave me exposure industry-level EDA tools and also understanding and appreciating the intricate trade-offs among area, power, and performance. Alongside this, I contributed to a Reconfigurable Intelligent Surface (RIS) project under Dr. Karun Rawat, where I worked on the control architecture and signal routing framework for dynamic beam reconfiguration. Additionally, under the guidance of Dr. XXX, I developed an ECG monitoring system involving Embedded C programming for signal acquisition, processing, and display. These experiences have deepened my interest in VLSI and embedded system design, reinforcing my aspiration to contribute to the advancement of efficient and intelligent integrated circuits.
I am particularly excited about the work of Digital Circuit and Systems research group, led by Prof. Luca Benini, whose work constitutes a perfect match for my long-term interest in low-power digital design, heterogeneous compute architectures, and memory-centric accelerators. Its PULP (Parallel Ultra-Low Power) platform stands out to me as a brilliant demonstration of how parallelism, tightly coupled RISC-V clusters, and domain-specific accelerators can provide high performance with a high energy efficiency, My coursework in Computer Architecture and hands-on design experience have given me a deep appreciation for the role of parallel execution and energy efficiency. Among the group's current efforts, FRACTAL project which focuses on fast and resilient architectures for cognitive tasks in energy-limited environments. With its goal of scalable, low-power AI inference at the edge, it is very aligned with my aspiration to work at the intersection of efficient compute, memory hierarchy optimization, and system-level VLSI design. Having designed a custom SPI interface IC in TSMC 65 nm through the full RTL-to-GDSII flow, device-aware insights from TCAD simulations, and fabrication knowledge from Indo-Taiwan Semiconductor Workforce Development Program, I find a natural synergy with the vision of this group in pushing the frontiers of ultra-efficient computing through innovative circuit and system co-design
In conclusion, I am determined to deepen my expertise in circuit design, with a particular focus on optimizing performance, power efficiency, and cost-effectiveness through advancements in transistor technologies and emerging design paradigms such as 3D IC integration. I aspire to contribute to the development of circuits that achieve higher computational density and lower energy footprints-bridging innovation with practicality. The knowledge and research exposure I have gained thus far, coupled with the opportunities offered by a master's program, will enable me to make meaningful and lasting contributions to the field. I believe that the skills, insights, and collaborative experience gained from this program will empower me to translate theoretical understanding into impactful, real-world innovations, advancing both my technical proficiency and the broader landscape of modern semiconductor design.
I would be grateful for suggestions on:
1) Whether the narrative feels too long or detailed
2) What parts seem strongest or weakest
3) Any redundancy or unclear paragraphs
4) Whether the motivation + technical depth is convincing
5) How I can improve flow or impact for graduate admissions
6) For submission to other colleges can i just rephrase the last two paragraphs
I have written a motivational letter for my Master's application in Electrical and Computer Engineering, with a strong focus on VLSI and Digital Design. I would appreciate honest, detailed feedback regarding the structure, clarity, flow, and impact overall, including how well it conveys motivation and technical readiness.
Full Motivational Letter:
My fascination with electronic systems began in childhood, when I would often visit my father's computer sales and service business out of curiosity, watching how components like the CPU, GPU, and memory together powered entire systems. Those early observations sparked a lasting passion to understand how complex electronic architectures emerge from the interaction of such fundamental building blocks. Over time, this curiosity evolved into a deep interest in understanding how devices are built-from the physics of transistors to the architecture of complex systems-and how every advancement in semiconductor fabrication presents new challenges and opportunities for circuit designers to innovate. Visiting semiconductor cleanrooms in India and Taiwan reinforced this realization, as I witnessed the immense precision and difficulty involved in pushing technology toward ever smaller and more efficient scales. The constant drive to optimize circuits by reducing power consumption, minimizing component size, and improving performance speed gives this field a distinct edge and limitless potential for innovation. This relentless pursuit of improvement appeals to the engineer and problem-solver in me, motivating me to deepen my expertise in Electrical and Computer Engineering. Through my academic journey and internship experiences, I have realized that this domain demands a profound level of expertise to make significant contributions. To bridge the gap between theoretical advancements and practical implementations and to fulfil my aspiration of driving innovation in circuit design, I aim to pursue a master's degree that will equip me with advanced knowledge, cutting-edge skills, and practical exposure to enhance the impact of my work in this domain.
My primary areas of interest include VLSI, Digital Logic Design, and Embedded Systems. As an undergraduate student in Electronics and Communication Engineering at IIT Roorkee, my journey began with foundational courses such as Analog Circuits, Digital Logic Design, and Microelectronic Devices and IC Applications These courses helped me develop a strong conceptual understanding of circuit design, device behaviour, and embedded architectures. In these courses, through various projects, I explored full-custom VLSI design using Cadence Virtuoso, where I created schematic layouts and performed DRC, LVS, and PEX verification for logic gates, flip-flops, and ring oscillators using 180nm technology. I also designed a two-stage CMOS operational amplifier in LTSpice and carried out PMOS simulations in Synopsys Sentaurus TCAD, analysing threshold voltage, subthreshold slope, and DIBL variations across technology nodes-an experience that strengthened my grasp of the trade-offs between performance, power, and area in modern circuits. Moving from transistor-level design to digital implementation, I developed the RTL design of combinational and sequential logic circuits using Verilog, verified them on FPGA platforms, and gained insights into timing optimization, resource mapping, and custom block design. My understanding of embedded architectures deepened as I programmed the 8085 microprocessors, which strengthened my understanding of instruction-level execution and embedded control. Furthermore, I co-developed a real-time passenger counting system using edge computing and deep learning-an innovation that led to a patent publication (IN202411xxxx). This project's blend of algorithm design, embedded hardware, and system integration reinforced my interest in complete electronic system development.
A defining moment in my journey was being selected among 25 students nationwide for the Indo-Taiwan Semiconductor Workforce Development Program, jointly conducted by XXX and National Tsing Hua University (NTHU), Taiwan. Under the mentorship of TSMC engineers and NTHU professors, I gained hands-on exposure to semiconductor fabrication processes, lithography, and advanced packaging techniques such as CoWoS, FOWLP, and 3D IC stacking. Observing the precision and challenges of sub-nanometre fabrication deepened my appreciation for how fabrication constraints drive innovation in circuit design, strengthening my resolve to specialize in VLSI design. Beyond academics, I served as the Joint Secretary of ASME IIT Roorkee, where I led projects integrating electronics, control systems, and embedded hardware. Working with Raspberry Pi, Arduino, hardware accelerators, and Pixhawk autopilot modules, I helped develop an Autonomous Underwater Vehicle (AUV) for international competitions. Our team achieved 2ⁿᵈ place in India and 8ᵗʰ globally at SAUVC 2024, an experience that honed my collaborative problem-solving and system-level thinking.
Building on the insights gained, I am currently working on my B.Tech project which focuses on the design of an SPI interface chip in TSMC 65 nm technology under the supervision of Dr.XXX encompassing the full RTL-to-GDSII design flow. I successfully implemented the RTL design as per the required specifications using Verilog in Xilinx Vivado, verified it through simulation, and deployed it on an FPGA platform for functional validation. The design was later synthesized using Cadence Genus, followed by floor planning, placement, and routing, and I am currently working on Clock Tree Synthesis and its optimization to minimize skew and power consumption, This gave me exposure industry-level EDA tools and also understanding and appreciating the intricate trade-offs among area, power, and performance. Alongside this, I contributed to a Reconfigurable Intelligent Surface (RIS) project under Dr. Karun Rawat, where I worked on the control architecture and signal routing framework for dynamic beam reconfiguration. Additionally, under the guidance of Dr. XXX, I developed an ECG monitoring system involving Embedded C programming for signal acquisition, processing, and display. These experiences have deepened my interest in VLSI and embedded system design, reinforcing my aspiration to contribute to the advancement of efficient and intelligent integrated circuits.
I am particularly excited about the work of Digital Circuit and Systems research group, led by Prof. Luca Benini, whose work constitutes a perfect match for my long-term interest in low-power digital design, heterogeneous compute architectures, and memory-centric accelerators. Its PULP (Parallel Ultra-Low Power) platform stands out to me as a brilliant demonstration of how parallelism, tightly coupled RISC-V clusters, and domain-specific accelerators can provide high performance with a high energy efficiency, My coursework in Computer Architecture and hands-on design experience have given me a deep appreciation for the role of parallel execution and energy efficiency. Among the group's current efforts, FRACTAL project which focuses on fast and resilient architectures for cognitive tasks in energy-limited environments. With its goal of scalable, low-power AI inference at the edge, it is very aligned with my aspiration to work at the intersection of efficient compute, memory hierarchy optimization, and system-level VLSI design. Having designed a custom SPI interface IC in TSMC 65 nm through the full RTL-to-GDSII flow, device-aware insights from TCAD simulations, and fabrication knowledge from Indo-Taiwan Semiconductor Workforce Development Program, I find a natural synergy with the vision of this group in pushing the frontiers of ultra-efficient computing through innovative circuit and system co-design
In conclusion, I am determined to deepen my expertise in circuit design, with a particular focus on optimizing performance, power efficiency, and cost-effectiveness through advancements in transistor technologies and emerging design paradigms such as 3D IC integration. I aspire to contribute to the development of circuits that achieve higher computational density and lower energy footprints-bridging innovation with practicality. The knowledge and research exposure I have gained thus far, coupled with the opportunities offered by a master's program, will enable me to make meaningful and lasting contributions to the field. I believe that the skills, insights, and collaborative experience gained from this program will empower me to translate theoretical understanding into impactful, real-world innovations, advancing both my technical proficiency and the broader landscape of modern semiconductor design.
I would be grateful for suggestions on:
1) Whether the narrative feels too long or detailed
2) What parts seem strongest or weakest
3) Any redundancy or unclear paragraphs
4) Whether the motivation + technical depth is convincing
5) How I can improve flow or impact for graduate admissions
6) For submission to other colleges can i just rephrase the last two paragraphs
